Semiconductor device

ABSTRACT

A semiconductor device includes first and second semiconductor regions, and a third semiconductor region between the first and second semiconductor regions, wherein the dopant concentration of the third semiconductor region is greater than the dopant concentration of the second semiconductor region. The semiconductor device further includes a fourth semiconductor region selectively provided on an upper surface of the second semiconductor region, wherein a portion of the second semiconductor region is interposed between the third semiconductor region and the fourth semiconductor region, an insulating layer disposed on the second semiconductor region and the fourth semiconductor region and having an opening that exposes a portion of a top surface of the fourth semiconductor region, wherein the ratio of an area of opening to an area of the top surface is from 10% to 90%, and a wiring layer on the insulating layer and connected to the fourth semiconductor region via the opening.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2014-196403, filed Sep. 26, 2014, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device.

BACKGROUND

In general, a PN diode is used as an element configuring an ESDprotection circuit in a semiconductor device which includes the ESDprotection circuit. In addition, breakdown of the PN diode is used as amethod of ESD protection in some cases.

Here, the PN diode which configures the ESD protection circuit isgenerally element-separated in the semiconductor device, i.e., it isisolated from the device it is protecting. As a method ofelement-separating the PN diode in the semiconductor device, there is amethod of element-separating the PN diode using a dopant diffused layer.However, to form the dopant diffused layer, an extended time period ofheat treatment must be performed. Therefore, the dopant is thermallydiffused in the semiconductor layer, such that a distribution of adopant concentration in a PN junction becomes moderate in some cases.

When the distribution of the dopant concentration in the PN junctionbecomes moderate, a breakdown voltage of the PN diode is unlikely to belowered. Therefore, a clamp voltage of a protection circuit provideddownstream of the ESD protection circuit is unlikely to be lowered.

DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic view which illustrates a main part of asemiconductor device according to an embodiment taken along line IA-IAof FIG. 1B. FIG. 1B is a schematic cross-sectional view whichillustrates the main part of the semiconductor device according to theembodiment taken along line IB-IB of FIG. 1A.

FIG. 2 is an equivalent circuit diagram of a circuit incorporated in thesemiconductor device according to the embodiment.

FIG. 3 is a block diagram which illustrates an example of a use of thesemiconductor device according to the embodiment.

FIG. 4A is a graph which illustrates a change in an dopant concentrationin the vicinity of a PN junction when an dopant concentration profile ona P-side of a zener diode D3 of the semiconductor device according tothe embodiment is changed, and FIG. 4B is a graph which illustrates acurrent-voltage curve of a zener diode breakdown when the dopantconcentration profile on the P side of the zener diode D3 of thesemiconductor device according to the embodiment is changed.

FIG. 5 is a graph which illustrates a dopant concentration in thevicinity of the PN junction when an inclination of the dopantconcentration profile on the P-side of the zener diode D3 of thesemiconductor device according to the embodiment is changed.

FIG. 6A is a dopant concentration profile in a depth direction of asemiconductor device according to a reference example, and is a graphwhich illustrates a dopant concentration taken along line X-Y of FIG.6B. FIG. 6B is a schematic cross-sectional view which illustrates thesemiconductor device according to the reference example.

FIG. 7A is a dopant concentration profile in the depth direction of thesemiconductor device according to the embodiment, and is a graph whichillustrates a dopant concentration taken along line X-Y of FIG. 7B. FIG.7B is a schematic cross-sectional view which illustrates thesemiconductor device according to the embodiment.

FIG. 8A is a graph which illustrates a current-voltage curve when aparasitic NPN transistor present in the semiconductor device operates ordoes not operate, and FIG. 8B is a schematic cross-sectional view whichdescribes an example of a factor for which the parasitic NPN transistorpresent in the semiconductor device operates.

FIG. 9A is a schematic plan view which illustrates a PN diode D2 and thezener diode D3 of the semiconductor device according to the embodiment,and is a view which illustrates a section taken along line IXA-IXA ofFIG. 9B. FIG. 9B is a schematic cross-sectional view which illustratesthe PN diode D2 and the zener diode D3 of the semiconductor deviceaccording to the embodiment, and is a view which illustrates a sectiontaken along line IXB-IXB of FIG. 9A. FIG. 9C is a graph whichillustrates a current-voltage curve of the PN diode D2 and the zenerdiode D3 of the semiconductor device according to the embodiment.

DETAILED DESCRIPTION

Exemplary embodiments provide a semiconductor device which enables ESDprotection by lowering a breakdown voltage.

In general, according to one embodiment, a semiconductor device includesa first semiconductor region of a first conductivity type, a secondsemiconductor region of a second conductivity type that is provided onthe first semiconductor region, a third semiconductor region of a secondconductivity type that is provided between the first semiconductorregion and the second semiconductor region, and in which a bottomthereof is in contact with the first semiconductor region, a portion ofa top on a side opposite to the bottom is in contact with the secondsemiconductor region, and a dopant concentration thereof is higher thanan dopant concentration of the second semiconductor region. The devicefurther includes a fourth semiconductor region of a first conductivitytype that is selectively provided on a surface of the secondsemiconductor region on a side opposite to the first semiconductorregion, and includes a portion of the second semiconductor regioninterposed between the third semiconductor region and the fourthsemiconductor region, an insulating layer that is provided on the secondsemiconductor region and the fourth semiconductor region and having afirst opening that exposes a portion of a top surface of the fourthsemiconductor region, wherein a ratio of an area of the portion to anarea of the top surface is from 10% to 90%, and a wiring layer that isprovided on the insulating layer and connected to the fourthsemiconductor region via the first opening.

Hereinafter, each embodiment will be described with reference to thedrawings. In addition, in the following description, the same referencenumerals are applied to the same members, and a description of memberswhich are described once will be appropriately omitted.

FIG. 1A is a schematic view which illustrates a main part of asemiconductor device according to an embodiment taken along line IA-IAof FIG. 1B. FIG. 1B is a schematic cross-sectional view whichillustrates the main part of the semiconductor device according to theembodiment, and is a view which illustrates a section taken along lineIB-IB of FIG. 1A.

In a semiconductor device 1 according to the embodiment, a plurality ofESD protection diodes (hereinafter, for example, PN diodes D1, D2, and azener diode D3, all shown in FIG. 1B) are provided. A circuit isprovided in the semiconductor device 1 by combining the PN diode D1 inparallel with the series connection of diode D2, and the zener diode D3.

The semiconductor device 1 includes a first semiconductor region(hereinafter, for example, a semiconductor region 20), a secondsemiconductor region (hereinafter, for example, a semiconductor region30), a third semiconductor region (hereinafter, for example, asemiconductor region 33), a fourth semiconductor region (hereinafter,for example, a semiconductor region 32), a fifth semiconductor region(hereinafter, for example, a semiconductor region 35), a sixthsemiconductor region (hereinafter, for example, a semiconductor region34), a seventh semiconductor region (hereinafter, for example, asemiconductor region 36), an eighth semiconductor region (hereinafter,for example, a semiconductor region 37), a wiring layer 10, aninsulating layer 70, and a protection film 71.

The semiconductor region 20 is a semiconductor substrate of thesemiconductor device 1. A conductivity type of the semiconductor region20 is an N⁺⁺-type. The semiconductor region 20 contains arsenic (As) orantimony (Sb) as dopants thereof. Furthermore, the semiconductor region20 may be doped with phosphorus (p).

The semiconductor region 30 is provided on the semiconductor region 20.A conductivity type of the semiconductor region 30 is a P⁻-type. Thesemiconductor region 30 is in contact with the semiconductor region 20.The semiconductor region 30 is, for example, an epitaxially grown layerformed on the semiconductor region 20.

The semiconductor region 33 is selectively provided between thesemiconductor region 20 and the semiconductor region 30, such that toeither side thereof, semiconductor regions 20 and 30 may be in contactwith one another. For example, a bottom 33 b of the semiconductor region33 is in contact with the semiconductor region 20, and a portion of atop 33 u of a side opposite to the bottom 33 b is in contact with thesemiconductor region 30. A conductivity type of the semiconductor region33 is a P⁺-type. The semiconductor region 33 is in contact with thesemiconductor region 20 and the semiconductor region 30. A dopantconcentration of the semiconductor region 33 is higher than a dopantconcentration of the semiconductor region 30. The zener diode D3 isconfigured of the semiconductor region 33 and the semiconductor region20.

The semiconductor region 32 is selectively provided on a surface of thesemiconductor region 30 on the side thereof opposite to the interfaceregion of semiconductor region 30 and semiconductor region 20. Aconductivity type of the semiconductor region 32 is an N⁺-type. Aportion of the semiconductor region 30 extending over the upper surface33 u of the semiconductor region 33 extends between the semiconductorregion 32 and the semiconductor region 33. The semiconductor region 32is in contact with the semiconductor region 30. The PN diode D2 isconfigured of the semiconductor region 32 and the semiconductor region30.

The semiconductor region 35 is selectively provided between thesemiconductor region 20 and the semiconductor region 30. For example, abottom 35 b of the semiconductor region 35 is in contact with thesemiconductor region 20, and a portion of a top 35 u of thesemiconductor region 35 on a side opposite to the bottom 35 b thereof isin contact with the semiconductor region 30. A conductivity type of thesemiconductor region 35 is an N⁺-type. The semiconductor region 35 isselectively provided between the semiconductor region 20 and thesemiconductor region 30 where the semiconductor region 33 is notprovided, and is spaced therefrom by an interface region between thesemiconductor region 20 and the semiconductor region 30. Thesemiconductor region 35 is in contact with the semiconductor region 20and the semiconductor region 30. The dopant concentration of thesemiconductor region 35 is lower than the dopant concentration of thesemiconductor region 20. The PN diode D1 is configured with thesemiconductor region 35 and the semiconductor region 30.

The semiconductor region 34 is selectively provided on a surface of thesemiconductor region 30 on a side thereof opposite to the side of thesemiconductor region 30 in contact with semiconductor region 20 betweensemiconductor regions 33, 35. The conductivity type of the semiconductorregion 34 is a P⁺-type. The semiconductor region 34 is selectivelyprovided on the surface of the semiconductor region 30 at a locationthereof where the semiconductor region 32 is not provided. A portion ofthe semiconductor region 30 on the semiconductor region 35 extendsbetween the semiconductor region 34 and the semiconductor region 35.

The semiconductor region 36 is provided on the semiconductor region 33.The semiconductor region 36 is in contact with the semiconductor region30 located on the semiconductor region 33. The semiconductor region 36surrounds the portion of the semiconductor region 30 located on thesemiconductor region 33 (FIG. 1A). The conductivity type of thesemiconductor region 36 is a P⁺-type. The semiconductor region 36 isconnected to, and contacts, the semiconductor region 33. Thesemiconductor region 36 forms or creates an element separation region inwhich the PN diode D2 and the zener diode D3 are separated from thesemiconductor region 30.

The semiconductor region 37 is provided on the semiconductor region 35.The semiconductor region 37 is in contact with the semiconductor region30 on the semiconductor region 35. The semiconductor region 37 surroundsthe portion of the semiconductor region 30 located on the semiconductorregion 35 (FIG. 1A). The conductivity type of the semiconductor region37 is an N⁺-type. The semiconductor region 37 is connected to thesemiconductor region 35. The semiconductor region 37 forms or creates anelement separation region in which the PN diode D1 is separated from thesemiconductor region 30.

The semiconductor 33, the semiconductor region 32, the semiconductorregion 35, the semiconductor region 34, the semiconductor region 36, andthe semiconductor region 37 are dopant diffusion regions which areformed by an injection of dopant elements into the semiconductor region20 or the semiconductor region 30 and a heating.

The insulating layer 70 is provided on each of the semiconductor region30, the semiconductor region 32, the semiconductor region 34, thesemiconductor region 36, and the semiconductor region 37. A firstopening (hereinafter, for example, an opening 70 h 1) extends throughinsulating layer to expose a portion the top surface 32 u of thesemiconductor region 32 and a second opening (hereinafter, for example,an opening 70 h 2) extends through insulating layer 70 to expose aportion of a top surface 34 u of the semiconductor region 34, areprovided in the insulating layer 70.

A wiring layer 10 is provided on the insulating layer 70 and extendsinwardly of openings 70 h 1 and 70 h 2. The wiring layer 10 is connectedto the semiconductor region 32 via the opening 70 h 1. In addition, thewiring layer 10 is connected to the semiconductor region 34 via theopening 70 h 2.

The wiring layer 10 is in ohmic contact with the semiconductor region 32and the semiconductor region 34. The protection film 71 is provided oneach of the insulating layer 70 and the wiring layer 10.

A main component of each semiconductor region is, for example, silicon(Si). In addition, the main component of each semiconductor region maybe a silicon carbide (SiC), a nitride gallium (GaN). Moreover, in theembodiment, unless otherwise noted, an N-type (first conductivity type)dopant concentration is lowered in an order of N⁺⁺-type to N⁺-type. Inaddition, in the embodiment a P-type (second conductivity type) dopantconcentration is lowered in an order of p⁺-type to p-type.

As an N-type dopant element, for example, arsenic (As), antimony (Sb),phosphorus (p), or the like is applied. As a P-type dopant element, forexample, boron (B) or the like is applied.

A material of the wiring layer 10 is a metal which includes at least oneof the group of aluminum (Al), titanium (Ti), nickel (Ni), tungsten (W),gold (Au), and the like. In addition, a material of the insulating layer70 includes, for example, a silicon oxide, a silicon nitride, and thelike.

FIG. 2 is an equivalent circuit diagram illustrating a circuitincorporated in the semiconductor device according to the embodiment.

In the semiconductor device 1, a crowbar circuit is configured as anexample. For example, a set of diodes including, for example, a seriesconnection of the PN diode D2 and the zener diode D3 are connected inparallel with the PN diode D1. A potential of the semiconductor region20 is set to be a ground potential.

For example, when a negative transient voltage is applied to the wiringlayer 10, the PN diode D2 is biased in a forward direction, the zenerdiode D3 is biased in a reverse direction, and the PN diode D1 is biasedin the reverse direction, respectively.

The breakdown voltage of the zener diode D3 may be arbitrarily set.Accordingly, the breakdown voltage of the zener diode D3 is set to belower than the breakdown voltage of the PN diode D1, whereby a currentdoes not flow in the reverse direction in the PN diode D1, but flows inthe reverse direction in the zener diode D3. Accordingly, a transientcurrent (surge current) flows (arrow A) from the semiconductor region 20to the wiring layer 10 through the zener diode D3 and the PN diode D2.

On the other hand, when a positive transient voltage is applied to thewiring layer 10, the PN diode D2 is biased in the reverse direction, thezener diode D3 is biased in the forward direction, and the PN diode D1is biased in the forward direction, respectively. When a forwarddirection voltage of the PN diode D1 is set to be lower than a breakdownvoltage of the PN diode D2, a transient current flows (arrow B) from thewiring layer 10 to the semiconductor region 20 through the PN diode D1.

FIG. 3 is a block diagram which illustrates an example of a use of thesemiconductor device according to the embodiment.

The semiconductor device 1 is incorporated in, for example, anelectronic product 500. The electronic product 500 includes a protectioncircuit 501 in addition to an ESD protection diode (semiconductor device1). The protection circuit 501 is connected to a contactor 503. Thesemiconductor device 1 is provided between the protection circuit 501and the contactor 503. An electronic circuit 502 in the electronicproduct 500 is protected from an external transient current by thesemiconductor device 1 and the protection circuit 501. The contactor 503is, for example, an electronic part attached to the electronic product500.

For example, it is assumed that a transient current I flows into theelectronic product 500 from the contact 503. In this case, it isdesirable that the transient current I be preferentially absorbed by thesemiconductor device 1 rather than the protection circuit 501.Accordingly, it is difficult for the transient current I to flow in theprotection circuit 501 provided in a rear of the semiconductor device 1,thereby preventing the protection circuit 501 from being damaged.

In order that the transient current I is preferentially absorbed in thesemiconductor device 1, it is desirable that a dynamic resistance (Rdyn)of the semiconductor device 1, when the transient current I flows intothe semiconductor device 1, be low. For example, when the dynamicresistance of the semiconductor device 1 is high, the transient currentI is not absorbed in the semiconductor device 1, and the transientcurrent I flows in the protection circuit 501, whereby the protectioncircuit 501 itself may be damaged.

Furthermore, in order to lower a voltage applied to the protectioncircuit 501 to electrically protect the protection circuit 501, it isdesirable to lower an absolute value of a breakdown voltage VBR of thezener diode D3. Accordingly, the voltage (clamp voltage) applied to theprotection circuit 501 becomes lower.

However, when the absolute value of the breakdown voltage VBR of thezener diode D3 is lowered, it is necessary to sufficiently suppressleakage current which occurs when reverse bias is applied to the zenerdiode D3. Accordingly, a snap-back phenomenon within the semiconductordevice 1 is caused. Here, the snap back phenomenon refers to aphenomenon in which a current rise generally occurs in response to avoltage rise in a current-voltage curve, but when a voltage is increasedto exceed a certain voltage, a current is increased despite a loweringof the voltage. In the semiconductor device 1, the snap-back phenomenonis caused, whereby low resistance of the dynamic resistance is realized.

FIG. 4A is a graph which illustrates a change in an dopant concentrationin the vicinity of a PN junction when an dopant concentration profile ona P-side of the zener diode D3 of the semiconductor device according tothe embodiment is changed, and FIG. 4B is a graph which illustrates acurrent-voltage curve of a zener diode breakdown when the dopantconcentration profile on the P side of the zener diode D3 of thesemiconductor device according to the embodiment is changed.

A horizontal axis of FIG. 4A indicates a depth (μm) of the semiconductorregion 20 at which the dopant concentration is present, and a verticalaxis indicates a dopant concentration (atoms/cm³). In FIG. 4A, dopantconcentration profiles of arsenic (As), and boron (B) are illustrated.Moreover, in the embodiment, a dopant concentration at a point at whicha dopant concentration profile of arsenic (As) intersects with a dopantconcentration profile of boron (B) is defined as “intersectionconcentration”. With regard to boron (B), three examples in which theintersection concentration is changed are exemplified.

Here, when the X-axis location (depth of intersection) between curve B-2of an dopant concentration profile of boron (B) and a curve As of thedopant concentration profile of arsenic (As) is set as the referencedepth (0.0 μm), the location on the X axis (relative depth ofintersection) of the intersection between a curve B-1 of an dopantconcentration profile of boron (B) and the curve As of an dopantconcentration profile of arsenic (As) deviates by −0.2 μm from thereference location (As concentration of about 1×10¹⁹ atoms/cm²). Inaddition, the x axis location (relative depth of intersection) of anintersection between a curve B-3 of a dopant concentration profile ofboron (B) and the curve As of a dopant concentration profile of arsenic(As) in the X-axis deviates by +1.0 μm from the reference location (Bconcentration of about 1×10¹⁵ atoms/cm²). These deviation values areshown in parentheses after the reference line configuration for each Bconcentration is depicted. In addition, as these deviation values areshifted to a negative side, it means that the intersection concentrationincreases.

Here, an absolute value of a breakdown voltage (VBR) when the dopantconcentration profile of boron (B) is that depicted in curve B-3 isabout 9.1 V (current 1 mA), and an absolute value of a breakdown voltage(VBR) when the dopant concentration profile of boron (B) is the curveB-1 is about 7.2 V (current 1 mA). That is, it is known that theabsolute value of a breakdown voltage (VBR) decreases as theintersection concentration increases. As an example of the factor, it isconsidered that extension of a depletion layer in the vicinity of the PNjunction when a reverse bias is applied is suppressed as theintersection concentration increases.

Specifically, when a dopant concentration of the semiconductor region 20or a dopant concentration of the semiconductor region 33 in a junctionin which the semiconductor region 20 and the semiconductor region 33 arejoined is 1×10¹⁷ (atoms/cm³) or more, it is known that an absolute valueof a voltage VBR is about 7.2 to 7.6 V (at a current of 1 mA).

Moreover, in FIG. 4B, without changing the dopant concentration profileof arsenic (As), a current-voltage curve of a zener diode breakdown whenthe dopant concentration profile of boron (B) is changed is illustrated.Here, the smaller the number in parentheses, the higher the intersectionconcentration.

From the result, it is known that as the intersection concentrationincreases, the leakage current of the zener diode D3 becomes larger. Itis considered that this is because a width of forbidden band becomesnarrower as the intersection concentration increases. The leakagecurrent of the zener diode D3 is a current flowing before a breakdown ofthe zener diode D3 when applying a reverse bias to the zener diode D3.

For example, the intercept between the curve B-3 of the dopantconcentration profile of boron (B) and the curve As of the dopantconcentration profile of arsenic (As) is shifted on the x-axis by +1.0μm is about 9.4×10⁻¹¹ (A) (at a voltage of 3.3 V).

In contrast, an intersection between the curve B-1 of the dopantconcentration profile of boron (B) and the curve As of the dopantconcentration profile of arsenic (As) is positioned on the X-axis, acurrent value when a deviation from the reference is −0.2 μm isapproximately 9×10⁻¹⁰ (A) (at a voltage of 3.3 V), and the current valueis increased.

FIG. 5 is a graph which illustrates a dopant concentration in thevicinity of the PN junction when the slope of the dopant concentrationprofile on the P side of the zener diode D3 of the semiconductor deviceaccording to the embodiment is changed.

A horizontal axis of FIG. 5 is a distance (μm), and a vertical axis is adopant concentration (atoms/cm³).

In FIG. 5, an intersection concentration between each curve B-1′, B-2′,and B-3′ of the dopant concentration profile of boron (B) and the curveAs of the dopant concentration profile of arsenic (As) corresponds toapproximately 5×10¹⁸ (atoms/cm3). However, the slopes of the curves ofthe dopant concentration profile become steeper in an order of the curveB-1′, the curve B-2′, and the curve B-3′.

Here, the breakdown voltage VBR tends to be lower as the slope of thecurve representing the dopant concentration versus depth profile becomessteeper. For example, an absolute value of the breakdown voltage (VBR)when the dopant concentration versus depth profile of boron (B) isrepresented by curve B-1′ is about 7.7 V (current 1 mA), an absolutevalue of the breakdown voltage VBR when the dopant concentration versusdepth profile of boron (B) is represented by curve B-2′ is about 7.6 V(current 1 mA), and an absolute value of the breakdown voltage (VBR)when the of boron (B) is represented by curve B-3′ is about 5.3 V(current 1 mA). It is believed that this is because the extension of thedepletion layer in the vicinity of the PN junction when a reverse biasis applied is further suppressed as the dopant concentration profile ofboron (B) becomes steeper.

Furthermore, it is known that the leakage current of the zener diode D3is relatively decreased compared to when the intersection concentrationof boron and arsenic is changed. For example, the current value is about4.5×10⁻¹⁰ (A) (at a voltage of 3.3 V) when the dopant concentrationprofile of boron (B) is the curve B-3′, a current value is about4.6×10⁻¹⁰ (A) (at a voltage of 3.3 V) when the dopant concentrationprofile of boron (B) is the curve B-2′, and a current value is about3.6×10⁻¹⁰ (A) (at a voltage of 3.3 V) when the dopant concentrationprofile of boron (B) is the curve B-1′

FIG. 6A depicts the dopant concentration profile in a depth direction ofa semiconductor device according to a reference example, and illustratesa dopant concentration taken along line X-Y of FIG. 6B. FIG. 6B is aschematic cross-sectional view which illustrates the semiconductordevice according to the reference example. The dopant concentrationprofile is measured by, for example, SIMS.

In a semiconductor device 100 according to the reference example, aconductivity type of each semiconductor region is reversed to aconductivity type of the semiconductor device 1. That is, an N-typesemiconductor region of the semiconductor device 1 becomes a P-typesemiconductor region in the semiconductor device 100, and a P-typesemiconductor region of the semiconductor device 1 becomes an N-typesemiconductor region in the semiconductor device 100.

In the semiconductor device 100, a P⁺⁺-type semiconductor region 200 isused as a semiconductor substrate. An N⁻-type semiconductor region 300is formed on the semiconductor region 200 by the epitaxial growth. AnN⁺-type semiconductor region 330 is provided between the semiconductorregion 200 and the semiconductor region 300. The semiconductor region200 contains boron (B), and the semiconductor region 300 containsphosphorus (p).

Here, a diffusion coefficient of boron (B) in a silicon crystal ishigher than a diffusion coefficient of arsenic (As) in the siliconcrystal. Accordingly, boron (B) diffuses from the semiconductor region200 into the semiconductor region 300 during the process ofmanufacturing the semiconductor device 100. As a result, in thesemiconductor device 100, there is a possibility that the dopantconcentration profile of boron (B) in the zener diode D3 becomesmoderated, and leakage current of the zener diode D3 cannot besufficiently suppressed.

FIG. 7A illustrates the dopant concentration profile in the depthdirection of the semiconductor device according to the embodiment, andis a graph which illustrates the dopant concentration taken along lineX-Y of FIG. 7B. FIG. 7B is a schematic cross-sectional view whichillustrates the semiconductor device according to the embodiment. Thedopant concentration profile is measured by, for example, the SIMS.

In contrast to the reference semiconductor device 100, an N⁺⁺-typesemiconductor region 20 is used as a semiconductor substrate in thesemiconductor device 1 according to the embodiment. The semiconductorregion 20 contains arsenic (As) as the n type dopant.

Accordingly, during a process of manufacturing the semiconductor device1, arsenic (As) is unlikely to be diffused from the semiconductor region20 to the semiconductor region 30, and the dopant concentration profileof boron (B) in the zener diode D3 becomes steeper than in thesemiconductor device 100. Accordingly, it is possible to reduce abreakdown voltage and to suppress the leakage current of the zener diodeD3 in the semiconductor device 1, compared to the leakage current in thesemiconductor device 100

Furthermore, in the semiconductor device 1 according to the embodiment,a parasitic NPN transistor present in the semiconductor device 1operates and a carrier in the semiconductor device 1 is increased,thereby further reducing the clamping voltage.

FIG. 8A is a graph which illustrates a current-voltage curve when aparasitic NPN transistor present in the semiconductor device operates ordoes not operate, and FIG. 8B is a schematic cross-sectional view whichdescribes an example of a factor for which the parasitic NPN transistorpresent in the semiconductor device operates.

Here, the current-voltage curve illustrated in FIG. 8A is acurrent-voltage curve of the PN diode D2 and the zener diode D3 whichare connected in series. The horizontal axis of FIG. 8A is a reversebias voltage. Moreover, in addition to the semiconductor device 1, acurrent-voltage curve of the semiconductor device 100 according to thereference example is illustrated in FIG. 8A as curve S.B.

In the semiconductor device 1, an NPN transistor is configured to havenot only the PN diode D2 and the zener diode D3, but also the N⁺-typesemiconductor region 32 (emitter)/the P⁻-type semiconductor region 30,and the P⁺-type semiconductor region 33 (base)/the N⁺⁺-typesemiconductor region 20 (collector).

When a voltage is applied between the N⁺-type semiconductor region 32,and the P⁻-type semiconductor region 30 and the P⁺-type semiconductorregion 33, whereby an electron (e) is injected in the P⁻-typesemiconductor region 30 and the P⁺-type semiconductor region 33 from theN⁺-type semiconductor region 32, a base current flows to turn on the NPNtransistor before a breakdown of the zener diode D3 in some cases. Thatis, in the semiconductor device 1, as illustrated in FIG. 8A, when avoltage (VR) is increased, a snap-back in which the voltage (VR) isfirst lowered and a current is increased occurs before the breakdown ofthe zener diode D3. As a result, a substantial breakdown voltage islowered in the semiconductor device 1.

In contrast, the parasitic NPN transistor is not embedded in thesemiconductor device 100 according to the reference example.Accordingly, a snap-back of the NPN transistor does not occur, but abreakdown voltage (curve VBR) of the semiconductor device 100 becomeshigher than a breakdown voltage of the semiconductor device 1.

FIG. 9A is a schematic plan view which illustrates the PN diode D2 andthe zener diode D3 of the semiconductor device according to theembodiment, and is a view which illustrates a section taken along lineIXA-IXA of FIG. 9B. FIG. 9B is a schematic cross-sectional view whichillustrates the PN diode D2 and the zener diode D3 of the semiconductordevice according to the embodiment, and is a view which illustrates asection taken along line IXB-IXB of FIG. 9A. FIG. 9C is a graph whichillustrates a current-voltage curve of the PN diode D2 and the zenerdiode D3 of the semiconductor device according to the embodiment.

The current-voltage curve illustrated in FIG. 9C is a current-voltagecurve of the PN diode D2 and the zener diode D3 connected in series. Ahorizontal axis of FIG. 9C indicates a voltage on a reverse bias side.FIG. 9C illustrates a change in snap-back when a ratio of an openingarea Sp to an area Sa of the top surface 34 u of the semiconductorregion 32 is changed.

As illustrated in FIG. 9C, as the opening area Sp of the opening throughthe insulating layer 70 through which the wiring layer 10 extends intocontact with the semiconductor region 32 becomes smaller in comparisonwith the area of the top surface 32 u of the semiconductor region 32,snap-back is more likely to occur. Accordingly, when an area of the topsurface 32 u of the semiconductor region 32 is Sa, and an area of aportion of the top surface 32 u opened by the opening 70 h 1 (FIG. 1B)is Sp, a ratio of Sp to Sa is adjusted to a range from 10% to 90%.

When the ratio of Sp to Sa is less than 10%, an opening of the N+-typesemiconductor region 32 becomes too small, and the contact resistancebetween the N⁺-type semiconductor region 32 and the wiring layer 10 isunacceptably increased.

In addition, when the ratio of Sp to Sa is larger than 90%, a voltagedrop is unlikely to occur between the wiring layer 10 side and thep⁻-type semiconductor region 30 side in the N⁺-type semiconductor region32. That is, a potential gradient (electric field) hardly occurs in theN⁺-type semiconductor region 32.

Accordingly, the electrons injected in the P⁻-type semiconductor region30 and the P⁺-type semiconductor region 33 from the N⁺-typesemiconductor region 32 are insufficient, a base current in the P⁻-typesemiconductor region 30 and the P⁺-type semiconductor region 33 isunlikely to increase. That is, the NPN transistor is unlikely to beturned on.

In this case, breakdown current becomes a base current to cause asnap-back after a breakdown of the zener diode D3. However, in thiscase, the clamping voltage is determined by a sole breakdown voltage ofthe zener diode D3, and the clamping voltage is not lowered in somecases.

As described above, in the embodiment, snap-back occurs by using theparasitic NPN transistor of the semiconductor device 1 to lower abreakdown voltage of the zener diode D3 and to suppress a leakagecurrent of the zener diode D3. Accordingly, it is possible to reduce aclamping voltage of a protection circuit connected to the semiconductordevice 1, thereby reliably ensuring ESD protection.

In the embodiment described above, “on” in an expression that “a portionA is provided on a portion B” is used to mean a case where the portion Adoes not come into contact with the portion B and the portion A isprovided above the portion B in addition to a case where the portion Acomes into contact with the portion B and the portion A is provided onthe portion B. Furthermore, “the portion A is provided on the portion B”may be applied to a case where the portion A and the portion Barereversed and the portion A is positioned below the portion B, or a casewhere the portion A and the portion B are horizontally provided in thesame line with each other. This is because the structure of thesemiconductor device is not changed between before and after therotation even if the semiconductor device according to the embodiment isrotated.

Hitherto, the embodiments are described with reference to the specificexamples. However, the embodiments are not limited to the specificexamples. That is, one in which those skilled in the art applyappropriate design changes to those specific examples is included in therange of the embodiments as long as it includes the characteristics ofthe embodiments. Each element included in the specific examples and, adisposition, a material, a condition, a shape, a size thereof, and thelike are not limited to those which are illustrated above and can beappropriately changed.

Furthermore, each of the elements included in each embodiment can becombined as long as it is technically possible and the combination isincluded in the range of the embodiments as long as each of the elementsincludes the characteristics of the embodiments. In addition, in acategory of the spirit of the embodiments, those skilled in the art canderive various modified examples and corrected examples, and themodified examples and the corrected examples are understood to be alsoincluded in the range of the embodiments.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A semiconductor device comprising: a firstsemiconductor region of a first conductivity type; a secondsemiconductor region of a second conductivity type that is provided onthe first semiconductor region; a third semiconductor region of a secondconductivity type that is provided between the first semiconductorregion and the second semiconductor region, and in which a bottomthereof is in contact with the first semiconductor region, a portion ofa top on a side opposite to the bottom is in contact with the secondsemiconductor region, and a dopant concentration thereof is higher thana dopant concentration of the second semiconductor region; a fourthsemiconductor region of a first conductivity type that is selectivelyprovided on a surface of the second semiconductor region on a sideopposite to the first semiconductor region, such that a portion of thesecond semiconductor region is interposed between the thirdsemiconductor region and the fourth semiconductor region; an insulatinglayer provided on the second semiconductor region and the fourthsemiconductor region, and comprising a first opening therethroughexposing a portion of a top surface of the fourth semiconductor region,wherein a ratio of an area of the portion of the top surface of thefourth semiconductor region exposed by the opening to the total area ofthe top surface is from 10% to 90%; and a wiring layer provided on theinsulating layer and connected to the fourth semiconductor regionthrough the first opening.
 2. The device according to claim 1, whereinat least one of the dopant concentration of the first semiconductorregion or the third semiconductor region at the junction of the firstsemiconductor region and the third semiconductor region is 1×10¹⁷(atoms/cm³) or more.
 3. The device according to claim 1, furthercomprising: a fifth semiconductor region of a first conductivity typeprovided between the first semiconductor region and the secondsemiconductor region, and in which a bottom thereof is in contact withthe first semiconductor region, and a portion of a top on a sideopposite to the bottom is in contact with the second semiconductorregion; and a sixth semiconductor region of a second conductivity typethat is selectively provided on a surface of the second semiconductorregion on a side thereof opposite to the first semiconductor region,such that a portion of the second semiconductor region is interposedbetween the fifth semiconductor region and the sixth semiconductorregion, wherein the dopant concentration of the fifth semiconductorregion is lower than the dopant concentration of the first semiconductorregion, a second opening in the insulating layer exposing a portion of atop surface of the sixth semiconductor region, wherein the wiring layeris connected to the sixth semiconductor region via the second opening.4. The device according to claim 3, further comprising: a seventhsemiconductor region of a second conductivity type located on the thirdsemiconductor region, and in contact with the second semiconductorregion on the third semiconductor region, wherein the seventhsemiconductor region is connected to the third semiconductor region. 5.The device according to claim 4, further comprising: an eighthsemiconductor region of a first conductivity type that is provided onthe fifth semiconductor region, and is in contact with the secondsemiconductor region on the fifth semiconductor region, wherein theeighth semiconductor region is connected to the fifth semiconductorregion.
 6. The device according to claim 1, wherein the firstsemiconductor region contains arsenic (As) or antimony (Sb).
 7. Thedevice according to claim 1, wherein the second semiconductor regioncontains phosphorous.
 8. An electrostatic discharge protection device,comprising: a semiconductor region of a first conductivity type; a firstPN diode disposed on and in electrical contact with the substrate; azener diode and second PN diode disposed on the substrate, the zenerdiode comprising the first semiconductor region of the firstconductivity type and a third semiconductor layer of the firstconductivity type, and the PN diode comprising a second semiconductorregion overlying the first semiconductor region such that the thirdsemiconductor region is selectively located therebetween and a fourthsemiconductor region of the first conductivity type having a surfacearea overlying a portion of the second semiconductor layer; and aninsulating layer overlying the PN diode and the Zener diode, theinsulating layer having a first opening therethrough extending to thesurface of the fourth semiconductor region and a second opening thereinextending to the first PN diode, wherein the ratio of the area of thefirst opening to the surface area of the fourth semiconductor region isgreater than or equal to ten percent and less than or equal to ninetypercent.
 9. The electrostatic discharge protection device of claim 8,further comprising: a conductor layer overlying the insulating layer andinto contact with the fourth semiconductor region and the first PNdiode.
 10. The electrostatic discharge protection device of claim 8,wherein the first pn diode is electrically connected in parallel to thesecond PN diode and the zener diode.
 11. The electrostatic dischargeprotection device of claim 10, wherein the second PN diode and the zenerdiode are electrically connected in series.
 12. The electrostaticdischarge protection device of claim 8, wherein the first semiconductorregion is a semiconductor substrate.
 13. The electrostatic dischargeprotection device of claim 12, wherein the semiconductor substrate is ndoped.
 14. The electrostatic discharge protection device of claim 8,wherein the pn diode comprises: a portion of the second semiconductorlayer; a fifth semiconductor region of the first conductivity typeinterposed between the first and second semiconductor layers; and asixth semiconductor region of the first conductivity type interposedbetween the second semiconductor region and the second opening.
 15. Theelectrostatic discharge protection device of claim 8, wherein the firstsemiconductor region is n doped.
 16. A method of providing electrostaticdischarge protection to a semiconductor device; comprising: providing afirst semiconductor region of a first conductivity type; forming a zenerdiode on a portion of the first semiconductor layer; forming a first PNdiode on the zener diode, the first PN diode comprising a portion of asecond semiconductor region of a second conductivity type overlying thefirst semiconductor layer, and a fourth semiconductor region of thefirst conductivity type overlying the second semiconductor region andhaving a surface area thereof; forming a second PN diode on the firstsemiconductor region; forming an insulating layer over the first andsecond pn diodes; and extending a first opening through the insulatinglayer to expose the fourth semiconductor layer, and forming a secondopening through the insulating layer to expose the second diode, whereinthe ratio of the area of the first opening to the surface area of thefourth semiconductor region is greater than or equal to ten percent andless than or equal to ninety percent.
 17. The method of claim 16,further comprising: providing a conductor over the insulating layer andin contact with the fourth semiconductor region and the second PN diode.18. The method of claim 16, further comprising: locating a thirdsemiconductor region of the second conductivity type between the portionof the first and second semiconductor layers underlying the firstopening.
 19. The method of claim 18, further comprising: providing afifth semiconductor region of the first conductivity type and having alower dopant concentration than the first semiconductor region betweenthe first and second semiconductor layers in a region underlying thesecond opening to form the second PN diode.
 20. The method of claim 19,further comprising: providing a sixth semiconductor region of the firstconductivity type between the second semiconductor region and the secondopening.